发明名称 |
Multiple level cache control system with address and data pipelines |
摘要 |
A cache controller for a system having first and second level cache memories. The cache controller has multiple stage address and data pipelines. A look-up system allows concurrent look-up of tag addresses in the first and second level caches using the address pipeline. The multiple stages allow a miss in the first level cache to be moved to the second stage so that the latency does not slow the look-up of a next address in the first level cache. A write data pipeline allows the look-up of data being written to the first level cache for current read operations. A stack of registers coupled to the address pipeline is used to perform multiple line replacements of the first level cache memory without interfering with current first level cache memory look-ups.
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申请公布号 |
US6021471(A) |
申请公布日期 |
2000.02.01 |
申请号 |
US19940340176 |
申请日期 |
1994.11.15 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
STILES, DAVID R.;ROTH, TERESA A. |
分类号 |
G06F12/08;(IPC1-7):G06F9/38 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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