发明名称 |
Combining plural data lines and clock lines into set of parallel lines and set of serial lines |
摘要 |
A data transfer system includes a plurality of functional blocks each provided with a function module for controlling data transfer between memories of the plurality of functional blocks, by being connected to a function module of other functional blocks via n sets of data signal lines and clock signal lines so that the data transfer proceeds in a synchronized manner. Each of the n sets of data signal lines and clock signal lines is appropriately combined with one another depending on a required condition for communicating with destination functional blocks, such that a plurality of sets of data signal lines and clock signal lines are used for parallel transfer and a single set of a data signal line and a clock signal line is used for serial transfer.
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申请公布号 |
US6021450(A) |
申请公布日期 |
2000.02.01 |
申请号 |
US19970923519 |
申请日期 |
1997.09.04 |
申请人 |
FUJITSU LIMITED |
发明人 |
YOSHIZAWA, JINICHI;NARA, HIROICHI;TAMURA, JUNICHI;HAYASHI, MASAO |
分类号 |
G06F13/16;G06F13/42;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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