| 摘要 |
PROBLEM TO BE SOLVED: To establish a PLL(phase locked loop) against the frequency of an inputted reference clock without changing a PLL circuit nor changing manually a circuit operation mode by preparing a division ratio varying part which discriminates the frequencies of plural input clocks to set a division ratio based on the discrimination result of frequencies and then divides the discriminated input clock. SOLUTION: A system clock SCLK is inputted to a timer circuit 1, and the circuit 1 is connected to a clock counter 2 and outputs a count time pulse T1 of a prescribed time width which counts input clocks ICLK, a latch pulse T2 which latches the clock calculation data and a reset pulse T3 which resets an internal circuit of the counter 2. The clocks ICLK which are inputted from the outside are inputted to the counter 2 and an input clock dividing circuit 4. The counter 2 is connected to a comparator circuit 3. |
