| 摘要 |
PURPOSE:To prevent a phase fluctuation of an output clock at the time of switching by generating a reproducing clock pulse by quantizing period data of a final period before switching instead of a period containing a switching time point, when a switching detecting signal is being inputted. CONSTITUTION:A frequency dividing part 30 frequency-divides one of clocks (CKs) 1-(n) selected by a selector 10, and a period quantizing part 40 detects a start and the next rise of 8KHzCK differentiated by a differentiating circuit. The quantizing part 40 counts the number of sampling (S) CKs during this time, and a reproducing part 50 loads data obtained by quantizing a period of the CK, counts SCK up to its value and reproduces the CK of 8KHz. Only when a switching signal is detected and a switching detecting part 20 outputs a signal of an H level, a reset pulse from the reproducing part 5 becomes valid, and a frequency dividing part 31 is reset. Accordingly, the frequency dividing part 31 starts a frequency dividing operation from an initial state, and in this case, the reproducing part 50 uses the previous quantizing data of the quantizing part 40. In such a way, a phase fluctuation of the output CK by switching can be prevented. |
