发明名称 INSTRUCTION CACHE DEVICE AND CONTROL METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To provide an instruction cache device storing the instruction block of a non-branch instruction and the instruction block of a branch destination instruction to dedicated first and second instruction caches and surely hitting the branch destination instruction in the second instruction cache and a control method therefor. SOLUTION: This instruction cache device 1 is provided with a first cache 5 for storing the instruction block taken out from an external memory, a second cache 6 for taking out the instruction block of the branch destination instruction from the external memory and storing it, an instruction decoder 10 for discriminating whether the instruction of the first cache 5 or the instruction of the second cache 6 is a branching instruction or the non-branching instruction, an address generation means 11 for generating the branch destination instruction address, and the next address of the next instruction in the case of the non- branch instruction or when the branching by the branch instruction is not established, a branch destination address register 9 for setting the branch destination instruction address of the address generation means 11 and a next address register 7 for setting the next instruction address.
申请公布号 JP2000029693(A) 申请公布日期 2000.01.28
申请号 JP19980200175 申请日期 1998.07.15
申请人 NEC SOFTWARE KOBE LTD 发明人 TAKEUCHI TAKAKAZU
分类号 G06F12/08;G06F9/38;(IPC1-7):G06F9/38 主分类号 G06F12/08
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