| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce noise due to a high-speed clock signal, while meeting the requirements of high-speed operation and low power consumption by controlling the state of a clock enable signal supplied to a synchronous DRAM in timing to the input and output of image data and controlling the operation stop and start states of a clock signal. SOLUTION: An image processing part 2 functions to write image data to a synchronous DRAM(SDRAM) 1 at a drawing request from a CPU 11 or read the image data out of the SDRAM1 at an output request. This device controls the state of the clock enable signal supplied to the SDRAM 1, in response to the input and output of the image data to and from the SDRAM1 used as a page memory and also controls the operation stop and start states of the clock signal supplied to the SDRAM1. Consequently, while no access request to the SDRAM1 is generated, the clock signal is in the operation stop state, and the clock signal will be transmitted only during the period required.</p> |
