| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the area of bulk tapping which is formed for impressing a bulk voltage by containing the bulk tapping in a plurality of dummy bit lines arranged in the columnar direction around a memory cell array and injecting a specific impurity into the dummy bit lines. SOLUTION: In order to reduce the level different between a memory cell array and its peripheral circuit, dummy word lines DW/L and dummy bit lines DE/L are arranged two lines by two lines around the cell array. The dummy bit lines DB/L are made of polysilicon containing an injected P+ impurity and formed for tapping areas. At the spot where the dummy bit lines DB/L and dummy word lines DW/L do not overlap each other, a contact area 1 to be connected to the source and drain of a cell transistor is replaced with a contact area 3 to be connected to a secondary well. The contact 3 can be used as a contact for bulk tapping.</p> |
