| 摘要 |
PROBLEM TO BE SOLVED: To reduce clock screw by employing a low resistance substance in a clock signal line connecting a signal source unit and a logic circuit unit. SOLUTION: Between a signal source unit, i.e., a clock signal source cell 101, and a logic circuit unit, i.e., a flip-flop cell 103, every plurality of stages of clock buffer cell 102 are connected through a clock signal line 104 of low resistance substance. Delay of bus is determined for each system by calculating delay for each net of the clock signal line 104 and a screw occurring for other bus is calculated. The line length is made uniform so that the screw is minimized and the number of drive is made uniform. According to the method, absolute clock screw can be reduced without modifying the route.
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