发明名称 HIEARCHICAL BUS SYSTEM AND BUS CONVERTER
摘要 PROBLEM TO BE SOLVED: To constitute a hierarchical bus system by mutually connecting a non-split type high speed bus and a low speed bus through a bus converter and to prevent the application efficiency of the high speed bus from being reduced. SOLUTION: The address of I/O device of which access time is longer than the overhead of a retrial response is stored in an inner register 10, and when an address comparator (A) 9 detects coincidene between an acceses address and one of addresses stored in the inner register 10 and the access is a reading access, a system bus (B) interface 16 starts the access and a system bus (A) interface 7 returns the retrial response to a bus master and temporarily opens a system bus (A) 100. When the end of the access has been returned at the time of a retrial access from the bus master, the bus master is informed of the end of the access, so that another access to the system bus (A) 100 can be permitted during the access of the I/O device having longer access time.
申请公布号 JP2000029824(A) 申请公布日期 2000.01.28
申请号 JP19980194459 申请日期 1998.07.09
申请人 HITACHI LTD;HITACHI PROCESS COMPUT ENG INC 发明人 YONEDA KENICHI;TOMIZAWA HIROSHI;INADA SHUNJI;NITTA MAKOTO
分类号 G06F13/36;G06F13/362;(IPC1-7):G06F13/36 主分类号 G06F13/36
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