| 摘要 |
PROBLEM TO BE SOLVED: To provide a cache memory system, capable of accelerating a cache error processing at writing of the large amount of data to successive addresses and accelerating the execution speed of a software including the cache error processing. SOLUTION: A normal write instruction (write and storage) 11, corresponding to a conventional cache control method and the write instruction 12 for a cache error are respectively prepared as being different instructions in the instruction set 10 of a general purpose processor 1. When the processing of the cache error is required, the write instruction 12 for the cache error updates a cache line 27 by write data, without reading the data from the address of a main memory 21 equivalent to a write address and sets both of the V-bit 24 and M-bit 25 of the line 27 to '1'.
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