发明名称 ADDER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a high-speed and area saving adder circuit for adding the binary number of (n) digits, the binary number of one digit and a constant '1'. SOLUTION: For the first input signal of (n) bits and the second input signal of one bit this circuit is provided with an OR circuit for obtaining the OR of the least significant bit 403 of the first input signal and the second input signal 450 and a NAND circuit for obtaining the AND of the OR output of the least significant bit of the first input signal and the second input signal and the second least significant bit of the first input signal.
申请公布号 JP2000029669(A) 申请公布日期 2000.01.28
申请号 JP19980195557 申请日期 1998.07.10
申请人 NEC CORP 发明人 YOSHIKAWA ATSUSHI
分类号 G06F7/501;G06F7/50;G06F7/505;(IPC1-7):G06F7/50 主分类号 G06F7/501
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