| 摘要 |
PROBLEM TO BE SOLVED: To provide a phase synchronizing circuit and a synchronizing method capable of compensating the delay time and reducing the power consumption. SOLUTION: The phases of an RCLK signal inputted from the outside and a fed back FCLK signal are measured by an enable signal, a measuring start signal (MB) and a measuring end signal (ME) are generated and while utilizing these two signals, delay time compensation cycle determine signals (MQ1, MQ 2...MQn) are outputted for the unit of each measuring unit. While receiving the RCLK dividing a frequency into two stages, RCLK signal, feedback FCLK signal and enable signal, delay time compensating signals (Q1, Q2...Qn) are generated corresponding to the delay time compensation cycle determine signals, RCLK is delayed and a phase synchronized clock signal (QCLK) is outputted. |
