SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DESIGNING CLOCK SUPPLY CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing both a clock skew and a power source system noise caused by the operation of a clock buffer. SOLUTION: This circuit controls the clock skew not for every clock buffer of the same step but so as to firstly equalize the delay of an entire clock path from a clock generating source (CG) to the clock input terminals of order circuits (FF1-FF7) and to secondly make mutually different the arrival of the clock at the clock buffer of the same step or to deviate the output inverting operation timing of the clock buffer of the same step. The clock skew is reduced by first one and the noise caused by the inverting output operation of the clock buffer is reduced by second one.