| 摘要 |
PROBLEM TO BE SOLVED: To enable reduction of a layout area in a CMOS circuit having a source diffusion layer and a well region having the same potential as the diffusion layer. SOLUTION: In a P channel MOS transistor having a P+ type source diffusion layer 22 and an N well region 12 both having an identical potential, for example, the source diffusion layer 22 and an N+ type substrate diffusion layer 23 of a diffusion region different in type from the layer 22 are formed on a surface of the N well region 12 at a location corresponding to the source region. A source contact 26 is provided to connect the source diffusion layer 22 and substrate diffusion layer 23 to an upper wiring layer via a salicide layer 24b. Since the source contact 26 is provided on the layer 23, the contact 26 can be positioned closer to the P well region 13.
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