发明名称 PIPELINED DUAL PORT INTEGRATED CIRCUIT MEMORY
摘要 PROBLEM TO BE SOLVED: To obtain a dual port RAM which is inexpensive and whose speed is high and whose capacity is large by providing an arbitration circuit judging which of first and second addresses is given to plural memories during the access to an integrated circuit memory to utilize single port RAMs. SOLUTION: A memory 20 includes a single port SRAM array 21, an arbitration circuit 24, bonding pads 26, 28, an input part 30 and an output part 50. At the time of an operation, the memory 20 functions as the static random access memory(SRAM) of a full dual port. The memory 20 generates an access request to the array 21 responding to an external access request. The arbitration circuit 24 assures that the earlier access request between two access requests is given to the array 21 except a time when the two access requests are actually received simultaneously and the priority is given to an X port when the requests are received simultaneously.
申请公布号 JP2000030460(A) 申请公布日期 2000.01.28
申请号 JP19990170696 申请日期 1999.06.17
申请人 MOTOROLA INC 发明人 ALAN S ROSS;NOGLE SCOTT GEORGE
分类号 G11C11/41;G11C7/00;(IPC1-7):G11C11/41 主分类号 G11C11/41
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