| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a burst synchronization circuit high in reliability and capable of selecting an optimum sampling phase by detecting both side edges of a 1-bit pulse without using an alternate pattern for burst synchronization in the case of matching a phase of a burst received data signal with a sampling phase of the received data signal and selecting an optimum sampling phase even on the occurrence of a bit error. SOLUTION: This burst synchronization circuit is provided with a data sampling section 11 that samples received data at pluralities of sampling phases whose phase difference is shorter than a one-bit period, a pattern detection section 12 that detects a prescribed pattern from the sampled data, a selection signal generating section 13 that selects an optimum sampling phase from the pattern detection result for each sampling phase, and a selector 14 that selects the sampled data at an optimum phase by the selection signal and provides an output of the selected data.</p> |
