| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the power consumption with a simple configuration. SOLUTION: When a flip-flop FF1 is set by the set instruction of a CPU 1, a flip-flop FF2 is set at the rising time of the next clock signal outputted from a buffer circuit BUF1 A flip-flop FF3 is set at the falling edge time of the next clock signal after the flip-flop FF2 is set, and an AND circuit AND2 outputs an operating clock signal to an internal circuit 3. After the CPU 1 resets the flip-flop FF1 by stop processing, the flip-flop FF2 is reset at the rising time of the next clock signal, the flip-flop FF3 is reset at the falling edge time of this clock signal, and the operating clock signal outputted from the AND circuit AND2 is stopped.</p> |
