发明名称 METHOD AND SYSTEM FOR DESIGNING INTEGRATED CIRCUIT LAYOUT INCLUDING METHOD FOR DETERMINING ARRANGING DIRECTION OF FUNCTIONAL BLOCK WHILE TAKING ACCOUNT OF INTERCONNECTION PERFORMANCE
摘要 PROBLEM TO BE SOLVED: To design an integrated circuit layout with minimum chip area by outputting an unplaceable indication when the rotational direction of a block does not clear other placement limitations otherwise performing inter-terminal routing by rotating the block to match a line and outputting a layout data. SOLUTION: Figure information is read in (S71) and a line indicative of the relation of placement between the center of block and a function block is calculated from the placing position of a large scale functional block in a chip, and distribution of terminal position of the large scale functional block thus determining the rotational direction of the block (S72-S74). A decision is then made whether the rotational direction of the block clears other placement limitations (S75) and an unplaceable indication is outputted when other placement limitations are not cleared (S79) otherwise the block is rotated to match a line (S76), inter-terminal routing is peformed (S77) and a layout data is outputted (S78).
申请公布号 JP2000031287(A) 申请公布日期 2000.01.28
申请号 JP19980201853 申请日期 1998.07.16
申请人 NEC CORP 发明人 OSANAI AYUMI
分类号 H01L21/822;H01L21/82;H01L27/04;(IPC1-7):H01L21/82 主分类号 H01L21/822
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