| 摘要 |
PROBLEM TO BE SOLVED: To provide a master/slave type flip-flop circuit of less power consumption and element number usable by single phase clock signals by providing a master side latch and a slave side latch respectively constituted of a logical gate and a latch means. SOLUTION: This circuit is composed of the master side latch 11 for inputting data signals DA, opposite phase data signals DA/ and clock signals CK and the slave side latch 12 connected to the output side of the master side latch 11. The master side latch 11 and the slave side latch 12 are respectively provided with the logical gates 20-1, 20-2 and 20-3 and 20-4 and the latch means 30-1 and 30-2 of a reset/set type. When the clock signals CK become L, the data signals DA are fetched to the latch means 30-1 inside the master side latch 11. When the clock signals CK become H, the fetched data signals DA are transmitted to the slave side latch 12 and outputted.
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