PROCESSOR, AND PIPELINE PROCESS CONTROL METHOD

摘要

PROBLEM TO BE SOLVED: To actualize accurate operation when instructions are executed through an instruction pipeline process including many stages by providing a pipeline process control means which controls processing at (n) stages between a 1st and a 2nd instruction. SOLUTION: An address arithmetic module 16 calculates the address of data to be accessed on an external memory. This address is generated by an automatic increment function. Further, an instruction decoder 17 decodes an instruction which is read out of the external memory and transmitted through an instruction bus to generate a control signal and totally controls an instruction pipeline process. Further, an instruction decoder 17 once judging that a decoded instruction is one of branch and return instructions of a program developed fro a four-stage instruction pipeline processor performs control for automatically inserting one hardware NOP instruction so that those instructions can accurately be executed on a five-stage instruction pipeline system.