发明名称 BUS HOLD CIRCUIT
摘要 PROBLEM TO BE SOLVED: To suppress a current which flows at the time of voltage variation of a bus to the minimum by allowing an output circuit to output a power source voltage when the output of a level detecting circuit is in a power source voltage area, generate a high impedance when it is in an intermediate voltage area, and output a ground voltage when it is in a ground voltage area. SOLUTION: The level detecting circuit 112 sections the voltage of a bus 3 into three levels from the power source voltage to the ground level to set the source voltage area, the intermediate voltage area, and the ground voltage area in order from the power source voltage side, and outputs their results. The output circuit 113 outputs the power source voltage when the output of the level detecting circuit 112 is in the power source voltage area. The output circuit 113 generates the high impedance when the output of the level detecting circuit 112 is in the intermediate voltage area. Further, the output circuit 113 outputs the ground voltage when the output of the level detecting circuit 112 is in the ground voltage area. Consequently, the current can be minimized in case of voltage variation of the bus 3.
申请公布号 JP2000029579(A) 申请公布日期 2000.01.28
申请号 JP19980194849 申请日期 1998.07.09
申请人 SEIKO EPSON CORP 发明人 HIUGA TSUTAE
分类号 G06F3/00;H03K19/0175;(IPC1-7):G06F3/00;H03K19/017 主分类号 G06F3/00
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