STATIC SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To realize a layout of memory cells which can further reduce a memory cell area according to an improvement in an element isolation technique. SOLUTION: The semiconductor memory device comprises CMOS memory cells each having two cross-coupled inverters each having N and P channel transistors connected in series. In this case at least one of contacts 15 and 16 of the two cross-coupled inverters are arranged outside a region sandwiched by source/drain diffusion parts of the N and P channel transistors in the memory cell.