发明名称 MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To improve the accuracy of connection between resist patterns, which are patterned by different lithography technologies of a lithography system which adopts lithographic technologies in combination. SOLUTION: An inspection pattern PQS, consisting of a 1st rectangular inspection pattern P1 which is patterned on a semiconductor wafer SW through a photolithography technology and a 2nd frame-shaped inspection pattern P2, which is pattern on the semiconductor wafer SW by an electron-beam lithography technology and arranged around the 1st inspection pattern P1, is used to inspect the matching of both 1st and 2nd resist patterns.
申请公布号 JP2000031014(A) 申请公布日期 2000.01.28
申请号 JP19980195777 申请日期 1998.07.10
申请人 HITACHI LTD 发明人 SATO KAZUHIKO
分类号 G03F9/00;G03F7/20;H01L21/027;(IPC1-7):H01L21/027 主分类号 G03F9/00
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