| 摘要 |
PROBLEM TO BE SOLVED: To generate a stable clock even in the case of using a voltage controlled oscillator(VCO) having a wide frequency variable area by outputting an exact control voltage corresponding to a phase difference between a reference signal and a compare signal to the VCO even when the phase difference is close to '0'. SOLUTION: Concerning a phase locked loop(PLL) circuit provided with a phase comparator 22, loop filter 24, VCO 14 and loop counter 26, a gate control signal Gc obtd. by advancing the phase of a compare signal Va by one clock is prepared, the phase comparator 22 is provided with a tree-state buffer for outputting the signals in three states corresponding to the phase difference of the signals Re and Va so as to be controlled into active state by the signal Gc, the timing to start the active state of the three-state buffer is quickened about by one clock more than a conventional case and even when any deviation of timing occurs between phase information and the gate control signal of the three-state buffer by signal transmission delay or the like, the front edge of phase information to the three-state buffer can be prevented from being omitted. |
