| 摘要 |
PROBLEM TO BE SOLVED: To shorten a test time especially at the time of testing a semiconductor memory concerning the semiconductor memory test. SOLUTION: A test mode circuit part 20 is constituted of a NAND gate L21, a NAND gate latch 21, and a buffer 22. The NAND gate 21 receives inputs of signals pt and bbu outputted from a parallel test circuit part, and operates an inverted AND. And, the NAND gate latch 21 receives an output of the NAD gate L21 and the signal pt as inputs, and outputs '0' signal only when the two inputs are '1', and the buffer 22 buffers this output of the NAD gate latch 21 to output a signal ttrb.
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