HIGHLY SELECTIVE AND COMPLETE INTERCONNECT METAL LINE AND VIA/CONTACT HOLE FILLING BY ELECTROLESS PLATING
摘要
<p>A novel method for the activation of semiconductor substrates for highly selective electroless copper plating in multilayer interconnect metallization lines and vias/contact holes has been developed. A copper-seeded polysilicon layer is provided over the substrate to facilitate growth of copper into the vias. Subsequent rinsing and chemical-mechanical polishing processes allow removal of overgrowth of copper and the polysilicon layer to achieve overall smooth topography of the copper surface and the insulating layer surface of the substrate.</p>
申请公布号
WO0004573(A1)
申请公布日期
2000.01.27
申请号
WO1999SG00076
申请日期
1999.07.14
申请人
NATIONAL UNIVERSITY OF SINGAPORE;LI, SAM, FONG, YAU;NG, HOU, TEE