Process and circuit to prevent excess erasing of digital memory using a control circuit that checks voltage in the memory and applies reduction

摘要

The memory (10) is coupled to a circuit (16) that applies an erase voltage. A control circuit (11) also operates with a second circuit to apply a reduced voltage. In operation a 12 V erase voltage is applied and a check is made that the erase voltage condition exists in the memory. If so the voltage is reduced to prevent excess erasure.