Semiconductor memory and the process used to handle fault conditions uses redundance selection lines coupled to the address decoder and a shift redundance circuit

摘要

The switching circuit (2) has a number of variable connections for decoder lines handling address signals. A number of selection and redundancy selection lines connect to the circuit to the decoder (5). The decoder connects to a control circuit (3) coupled to a shift register redundancy fuse circuit (4) that responds when a fault occurs in the selection lines.