| 摘要 |
A ferroelectric storage arrangement includes an array of memory cells comprising of a number of memory cells which have at least one selection transistor and a memory storage capacitor, and which are controlled via word-lines (WL) and via bit-lines (BL,bBL). A short circuit transistor (SG1,SG2) is bridged over each memory capacitor (CF1,CF2) and short-circuits the electrodes of the memory capacitor (CF1;CF2), or more specifically the short-circuit transistors (SG1,SG2) are connected in parallel to the memory capacitors (CF1,CF2).
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