PROCESSOR UNIT SUITABLE FOR DOUBLING

摘要

The invention relates to a master processing unit (MPU) which comprises a clock generator unit (CLK), a central processing unit (CPU), a user memory (MEM), a processor bus (PBU) and a bus control unit (BMI) which has an interface for a bus cross link (BXL) to at least one other master processing unit (MPU'). The bus control unit (BMI) via the processor bus (PBU) monitors the data access of the central processing unit (CPU) and via the bus cross link (BXL) exchanges data-access related signals, evaluates same and in accordance with the result of the evaluation emits an error signal. In a processor system (PSR) which consists of at least two master processing units (MPU, MPU') linked with each other via the bus cross link (BXL), the central processing units (CPU, CPU') of the master processing units (MPU, MPU') are started synchronously; every time the central processing units (CPU, CPU') access data the bus control units (BMI, BMI') of the master processing units (MPU, MPU') exchange signals via the bus cross links (BXL) and emit an error signal in case of a non-match. In case of an error in a master processing unit (MPU), operation of the processor system (PSR) is continued in the other master processing unit (MPU').