发明名称 Apparatus for performing a low latency memory read with concurrent snoop
摘要 A computer system has a system memory, cache memory, system controller that process memory transactions. The system controller transmits a memory request to the system memory without waiting for the cache memory to be snooped to determine whether the cache memory stores information in an address corresponding to a selected address of the system memory. The system controller may transmit a snoop request to the cache memory concurrently with or after the memory request is transmitted to the system memory. The system controller may have a control switch that uses a first pathway for the memory request and a second pathway for the snoop request so that the snoop and memory requests can be transmitted simultaneously.
申请公布号 US6018792(A) 申请公布日期 2000.01.25
申请号 US19970886908 申请日期 1997.07.02
申请人 MICRON ELECTRONICS, INC. 发明人 JEDDELOH, JOSEPH;MEYER, JAMES;BROWN, JEFFREY R.
分类号 G06F12/08;(IPC1-7):G06F12/00;G06F13/00 主分类号 G06F12/08
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