DELAY LOCK LOOP CIRCUIT

摘要

PURPOSE: A DLL(delay locked loop) circuit is provided to reduce time elapse until a lock-on state when the DLL circuit starts in a normal mode or resumes a normal mode from a standby mode. CONSTITUTION: The DLL circuit comprises: a variable delay circuit for variably delaying a first clock; a second clock created by delaying an output of the variable delay circuit for a predetermined amount of time; a phase comparator creating resultant signal of the phase comparison between the first clock and the second clock; a delay control circuit supplying a delay control signal for controlling delay time to the variable delay circuit in response to the resultant signal of the phase comparison. The delay control circuit creates a single delay control signal reducing the delay time of the variable delay circuit to a minimum for the normal mode of the DLL circuit and creates binary delay control signal modifying the delay time of the variable delay circuit to binary digit when the DLL circuit starts a normal mode. Therefore DLL circuit can go to a lock-on state in a short time because a phase control is carried out by a binary shift method during a start mode and stabilize because the phase control is performed by a single shift method during a normal mode.