| 摘要 |
PURPOSE: A test mode circuit is provided to certainly reset a test mode signal. CONSTITUTION: The test mode circuit comprises: a latch circuit(11) for latching a test enable signal(TE) and address signals(IA1, IA2,..., IAm); an input circuit(15) connected to a data mask terminal(DQM), for generating a mask signal(OEMSK) in response to a signal of the data mask terminal(DQM); a gate circuit(130 to 13m) connected to the latch circuit(11) and the input circuit(15), the gate circuit passing the test enable signal(TE) and the address signals(IA1 to IAm) latched in the latch circuit(11) when the mask signal(OEMSK) is inactivated and the gate circuit masking the test enable signal(TE) and the address signals(IA1 to IAm) latched in the latch circuit(11) when the mask signal(OEMSK) is activated; and a decoder circuit(12) connected to the gate circuit(130 to 13m), wherein the decoder circuit(12) responds to the test enable signal(OEMSK), decodes the address signals through the gate circuit, and generates one of test mode signals(TST1 to TSTm); and wherein the decoder circuit(12) resets the test mode signals(TST1 to TSTm) when the test enable signal and the address signals are masked.
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