| 摘要 |
A semiconductor memory device is grouped into a plurality of flexible macro chips. Under the circumstances, a clock input first stage circuit is arranged in a first flexible macro chip to supply an internal reference clock signal and a first internal clock signal in response to an external reference clock signal. Further, a group of command input first stage circuits are collectively arranged in a second flexible macro chip different from the first flexible macro chip. In this event, the the first internal clock signal is directly supplied to the command input first stage circuits so as to input a command signal.
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