| 摘要 |
PURPOSE: A semiconductor memory circuit is provided to reduce a data transfer time by reducing a capacitance of local and global data buses. CONSTITUTION: The semiconductor memory circuit comprises: a plurality of transfer selection parts(401, 411) for making tow pairs of transfer transistors of a plurality of pairs of transfer transistors(402-409, 412-419) being operate the same according to an output signal(Yd0, Yd1) from a column address decoder, wherein the transfer transistors of the pairs(402-409, 412-419) are coupled to corresponding pairs of bit lines(bit0/bit0b-bit7/bit7b) and control a signal transmission; at least two gate transistor pairs connected to at least two pairs of local data bus lines(ldb0/ldb0b-idb3/idb3b) and at least tow pairs of global data bus lines(gdb0/gdb0b-gdb3/gdb3b); and global data bus line sense amplifiers connected to at least two pairs of gate transistors(422-429), respectively.
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