DRAM HAVING A SELF-REFLASH CONTROL CIRCUIT AND SYSTEM LSI

摘要

PURPOSE: A DRAM having a self-reflash control circuit and system LSI is provided, which can voluntarily set a self-reflash period and can decrease consumption power when being a stand-by. CONSTITUTION: A DRAM having a self-reflash control circuit comprises: a memory cell array (1) having a plurality of memory cell; a data output buffer (1) for temporarily storing data stored in the memory cell array (10); a data input buffer (2) for temporarily storing an input data inputted to the memory cell array (10); a read/write control circuit (3); a column address generating circuit (4) for generating a column address of the memory cell in the memory cell array (10); a column decoder (5) for decoding the column address of the column address generating circuit (4); a sense amplifier and write driver (6); a self-reflash control circuit (7); a row address buffer (8); a row decoder (9); and a self-reflash address control unit (11) for generating an address for performing the self-reflash. Therefore, the self-reflash with a certain period can to easily set and an optimum self-reflash period can to be set.