| 摘要 |
PROBLEM TO BE SOLVED: To achieve delay calculation while suppressing the amount of calculation regardless of high accuracy by calculating a path and a net delay using the secular change of the delay value of input and output pins in the case of delay calculation considering the aging of the delay value due to hot electron effect. SOLUTION: Since the minimum unit in a logic level circuit is a logic block, information such as internal transistors or the like required for calculation needs to be provided independently as the element information in logic block units. Therefore, information such as a load capacity 112 and a waveform deterioration 114 caused by circuits inside the block, information on the size of N-channel transistors, coefficients for calculating the amount of delay deterioration, and the like are stored as the element information of input/output pins. The amount of delay deterioration of transistors Tr111 and Tr121 at the input/ output pin side is calculated from the values, frequencies 113 and 123 obtained by the calculation of a logic level circuit, and waveform distortion 114 and 124. The calculation delay values can be directly utilized for circuit simulation and static timing analysis.
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