发明名称 COMPILER, OPTIMIZING DEVICE, ASSEMBLER, LINKER, DEBUGGER, INVERSE ASSEMBLER AND PROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide a processor capable of executing a program in which units for reading and executing instructions are different and to provide a program development environment capable of preparing such the program. SOLUTION: When instruction decoders 409a-409c decode a branching instruction, high-order 29 bits of a PC relative value contained in this branching instruction are sent to a host PC computing element 411 and low-order 3 bits of the PC relative value are sent to a slave PC computing element 405. The slave PC computing element 405 adds or subtracts the current value of a slave PC 404 and the value of low-order 3 bits of the PC relative value and sends the operated result to the slave PC 404 as an update value. The host PC computing element 411 adds or subtracts the current value of the host PC 403 and the value of high-order 29 bits of the PC relative value or the number of carry from the slave PC computing element 405 as the case may be and sends the operated result to the host PC 403 as an update value.
申请公布号 JP2000020312(A) 申请公布日期 2000.01.21
申请号 JP19990120634 申请日期 1999.04.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TAKAYAMA SHUICHI;OGAWA HAJIME;KAWAGUCHI KENICHI;HIGAKI NOBUO;KOTANI KENSUKE;TANAKA TETSUYA;MIYAJI SHINYA;HEIJI TAKEHITO
分类号 G06F9/38;G06F9/30;G06F9/32;G06F9/45;G06F11/28;(IPC1-7):G06F9/38 主分类号 G06F9/38
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