发明名称 MULTIPROCESSOR SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a multiprocessor system capable of providing sure arbitrating operation to two processors. SOLUTION: An arbitration circuit fetches access requests from both the processors through flip-flop(FF) 1 and 3 at mutually different timing and sets/ resets an SR latch circuit FF 5 with the outputs of these FF1 and FF3. An OR gate OR1 ORs the outputs of FF1 and FF3 and the set output of the FF5 and an OR gate OR2 ORs the outputs of FF1 and FF2 and the reset output of FF5. The FF1 fetches the output of OR1 at the same clock timing as FF1 and permits access to one processor. An FF4 fetches the output of OR2 at the same clock timing as FF3 and permits access to the other processor.
申请公布号 JP2000020491(A) 申请公布日期 2000.01.21
申请号 JP19980185771 申请日期 1998.07.01
申请人 MEIDENSHA CORP 发明人 KOBAYASHI TETSUYA
分类号 G06F15/167;(IPC1-7):G06F15/167 主分类号 G06F15/167
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