| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit capable of reducing jitters in the cycle of clock signals, reducing the accumulation of the jitters even at a high multiplication rate and supplying stable clock signals. SOLUTION: Up signals Sup and down signals Sdw from a phase comparator are counted and a main counter 202 increases/decreases a counted value M corresponding to the counted result of an N-ry counter 206 for setting the counted value. A P counter 208 counts the clock signals PLCK outputted from a frequency multiplier, the counted value M of the main counter 202 is selected and outputted to the frequency multiplier by a selection circuit until the counted value reaches the counted value A of the N-ry counter 206 and an arithmetic value (M±1) is selected and outputted to the frequency multiplier while the counted value of the P counter 208 is from (A+1) to (N-1). Thus, the jitters in the oscillation signals PLCK of the frequency multiplier are reduced and the stable clock signals are supplied.
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