| 摘要 |
PROBLEM TO BE SOLVED: To secure the same transfer speed of data before and after interleave processing and to perform an even bit interleave operation by comprising a shift register of a specific number of stages and a plural-input/single-output multiplexer. SOLUTION: An interleave circuit consists of a shift register 1 which has [N×(N-1)+1] shift stages and performs an interleave operation of depth N and an (N+1)-input/single-output multiplexer 2. The register 1 has an output terminal for each of [N-(N-n)×(N-1)+1]-th stages counted from an input terminal (n=0, 1...N), and these output terminals are connected to (N+1) input terminals respectively. The multiplexer 2 switches the connection of output terminals of the register 1 in the order of the 1st stage, the [N×(N-1)+1]-th stage and the 1st stage again every time the data are inputted to the register 1 and then reads out the output to output it.
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