| 摘要 |
<p>PROBLEM TO BE SOLVED: To immediately supply an internal clock signal which is in phase synchronization with an external clock signal when recovering from a low power consumption mode to a normal mode by continuously keeping on generating the internal clock signal which is in phase synchronization with the external clock signal even in the low power consumption mode. SOLUTION: In an internal clock output circuit 102, an active command A/C is supplied, and a DLL circuit 11 continuously keeps on generating a delayed clock signal DLL-CLK which is in phase synchronization with an external clock signal E-CLK in an active powerdown mode in which a clock enable signal CKE is in an L level. Thus, when recovering from the active powerdown mode to a normal mode, the internal clock signal CLK which is in phase synchronization with the external clock signal E-CLK can be immediately supplied to an address buffer or the like, thereby resulting in a rapid transition of an SDRAM to the condition in which a wiring operation, a readout operation, or the like can be performed.</p> |
