| 摘要 |
PROBLEM TO BE SOLVED: To provide a test design method capable of making an integrated circuit efficient in design and low in cost by improving the processing procedures by applying a conventional library. SOLUTION: A flip-flop circuit library with a scanning function exclusive for logic synthesis is prepared at a step 11. The logic synthesis is performed only by a flip-flop circuit with the scanning function at a step 12. A floor plan is reviewed by performing arrangement, wiring and simultaneously synthesizing a clock tree by using a layout tool at a step 13. Based on a reviewing result of the floor plan, a logic circuit is completed by connecting a scan chain at a step 14. A test pattern is automatically generated by an ATPG tool at a step 15. In the case of full-scan design, a part to be a shift register in a normal operation mode is replaced with a flip-flop circuit without scanning function at a step 17.
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