| 摘要 |
PROBLEM TO BE SOLVED: To reduce both circuit scale and current consumption by preparing a circuit constitution where a slow clock is used as the clock input for a counter and a specific number of bits of the counter is decreased. SOLUTION: A mask circuit 8 generates a code series whose phase is delayed by a degree equivalent to the clock number that is decided by multiplying 512-offset value 3 corresponding to the mask value 2 by 64 by reading out the code series based on the value 2 stored previously in a ROM table and calculating the state of a 215-1 PN code generator 6. Meanwhile, a signal 14 that is generated by the circuit 8 is kept in a state where the data exceeding their necessity by the time equivalent to a single clock are outputted since the storage element of the generator 6 holds the data when the clock of the generator 6 is stopped. In order to avoid the above state, a comparator 10 is used to compare the count of a counter 15 which is in synchronism with the generator 6 and counts 0 to 511 with the value having its phase that is delayed a degree equivalent to the clock number corresponding to the value 3. |
