MATCHED FILTER CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a matched filter circuit capable of reducing the offset errors of matched filter output signals while considering the case that respective numbers of '+1' and '-1' in a PN code do not match each other for coping with the system of a long code. SOLUTION: In this matched filter circuit, a Vro1 generation circuit 15 outputs voltage signals at the time of refreshing the three-stage inverter of a sample-and-hold circuit 11, respective multipliers 13' select and output either signals inputted from the sample-and-hold circuit 11 or signals inputted from the Vro1 generation circuit 15 corresponding to the corresponding PN code and an adder 14 totals and outputs the signals inputted from the multipliers 13'.