Low impedance voltage source for powering integrated circuits uses linked MOS transistors in control and power stages to reduce power consumption to zero when no charge is received

摘要

The source comprises a power circuit (2) containing a first MOS transistor (T1) connected between the supply (Vdd) and the output terminals (Vo), with a second MOS transistor (T2) connected between the output and ground. The control circuit (5) also uses two series-connected MOS transistors (T3,T4') supplied through resistor R1, with connections between the supply, the grill and the base of transistor T4'. A second current through resistor R2 is supplied to transistor T3. The base of the transistors T3 is connected to ground. Conduction is avoided for the condition of Vo = Vdd/2 due to the combination of the inversion of transistors T3 and T4' and the interconnection of the collectors and source of transistor T4'. For the voltage Vdd equal to 2.5 Volts, the circuit allows the voltage of Vt1 and Ve2 of 1 volt, a voltage Vt4'of 0.63 volt and a voltage of Vt3' of 0.73 volts. In these conditions an interval exists of around 12 millivolts around the value of vdd/2 in which neither of the two transistors T1 and T2 of the power stage conduct.