HIGH PERFORMANCE SELF BALANCING LOW COST NETWORK SWITCHING ARCHITECTURE BASED ON DISTRIBUTED HIERARCHICAL SHARED MEMORY

摘要

A data switch for network communications includes at least one first data port interface (20) which supports a plurality of data ports which transmit and receive data at a first data rate. At least one second data port interface (30) is provided, which supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface (40) is provided, configured to communicate with a CPU. An internal memory (50) is provided, and communicates with the at least one first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface (70) for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel (80) is provided, with the channel communicating data between the at least one first data port interface, the at least one second data port interface, the internal memory, and the memory management unit.