Multiple data rate synchronous DRAM for enhancing data transfer speed

摘要

The present invention relates to a multiple data rate memory device which has broadened the concept of a double data rate SDRAM. The multiple data rate memory device includes clock signal generator means for receiving an external clock of a frequency f and outputting a plurality of clocks, a frequecy multi-doubler for logically operating the plurality of clocks and outputting an internal clock of a frequency 2Nf (N is natural number); an odd data input buffer for receiving tha data at the rising edge of the internal clock; and an even data input buffer for receiving tha data at the falling edge of the internal clock.