发明名称 Fuse-latch circuit having high integration density
摘要 A semiconductor IC apparatus including a fuse-latch unit. The fuse-latch unit comprises many fuses and latch output circuits. The fuses and the latch output circuits are arranged at pitches as short as possible, leaving virtually no dead spaces between them. The fuse-latch unit is therefore short in the direction the fuses and latch output circuits are arranged, thus occupying only a small area. The latch output circuits are arranged in two parallel columns. The fuses are arranged in one column extending between the two columns of latch output circuits. The fuses are connected, alternately to the latch output circuits of the first column and those of the second column.
申请公布号 US6016265(A) 申请公布日期 2000.01.18
申请号 US19980209120 申请日期 1998.12.10
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 YOSHIDA, MUNEHIRO;KOTANI, RYOUJI
分类号 H01L27/10;G11C17/16;(IPC1-7):G11C8/00 主分类号 H01L27/10
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