发明名称 |
Detecting long latency pipeline stalls for thread switching |
摘要 |
An apparatus is provided that operates in conjunction with a processor having registers and associated caches and a memory. A load management module monitors loads that return data to the registers, including bus requests generated in response to loads that miss in one or more of the caches. A cache miss register includes entries, each of which is associated with one of the registers. A mapping module maps a bus request to a register and sets a bit in a cache miss register entry associated with the register when the bus request is directed to a higher level structure in the memory system.
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申请公布号 |
US6016542(A) |
申请公布日期 |
2000.01.18 |
申请号 |
US19970001552 |
申请日期 |
1997.12.31 |
申请人 |
INTEL CORPORATION |
发明人 |
GOTTLIEB, ROBERT STEVEN;CORWIN, MICHAEL PAUL |
分类号 |
G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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